Research and teaching interests

  • Analog CMOS IC Design
  • Sensor Interfacing Circuits
  • Neuromorphic VLSI circuits
  • ASICs for bio-signal measurement
Devarshi Das

About me

I am an Assistant Professor in the Department of Electrical Engineering at the Indian Institute of Technology (IIT) Ropar, India. I have received an M.Tech degree from IIT Delhi in 2010 and a PhD degree from IIT Bombay in 2017. My PhD thesis focused on the design and development of low-power and low-noise analog signal conditioning integrated circuits. My PhD supervisor was Prof. Maryam Shojaei Baghini. From 2010 to 2012, I worked as a Design Engineer in the Advanced Technology Organisation (ATO) lab of General Electric (GE). From 2017 to 2018, I worked as a Lead Research Engineer in the Corporate Technology (CT) group of Siemens. My research interest is multidisciplinary, which includes CMOS integrated circuit design, AI-oriented circuits and systems, neuromorphic electronics, bio-medical instrumentation and sensors interfacing circuits. I have published more than 20 journal/conference papers as author/co-author and have filed for several patents. I am a senior member of IEEE and also an active reviewer for many reputed journals, including IEEE Journal of Solid State Circuits, IEEE Trans. on Circuits and Systems - 1, IEEE Trans. on Neural Networks and Learning Systems, IEEE Trans. on Biomedical Circuits and Systems, IEEE Trans. on Instrumentation and Measurements, IEEE Sensors Journal, Elsevier Microelectronics Journal, IET Electronics Letters and others. I was awarded as one of the "Outstanding Reviewers of 2019" by the IEEE Transactions on Instrumentation and Measurement Society. I served as the track chair for the Analog and Mixed Signal Design track & the Sensors Circuits and Systems track in VLSID 2022.

Academic background

  1. Ph.D., Indian Institute of Technology Bombay (IIT-B), Mumbai, India (2012-17)
  2. M.Tech., Indian Institute of Technology Delhi (IIT-D), New Delhi, India (2008-10)
  3. B.E., Faculty of Technology, DDU, Nadiad, India (2002-06)

Work experience

  1. IIT Ropar, Assistant Professor, 2018 - onwards
  2. Siemens, Lead Research Engineer, 2017-18
  3. General Electric, Design Engineer, 2010-12

Courses offered

  1. GE 108 - Basic Electronics (Theory) (Spring: 2021, 2022)
  2. EE 533 - CMOS Analog IC Design (Autumn: 2019, 2020, 2021)
  3. EE 537 - Circuits Simulation Lab (Autumn: 2019, 2020, 2021)
  4. EE 209 - Circuit Theory (Spring: 2020)
  5. EEL 323 - Measurements and Instrumentation (Spring: 2019)
  6. EE 204 - Digital Circuits Lab (Autumn: 2018, 2019)
  7. GE 108 - Basic Electronics (Lab) (Autumn: 2018; Spring: 2019, 2020,2022)

Current Ph.D. scholars

  1. Shivdeep
  2. R. K. Srivastava (Co-guide: Dr. Z. A. Khan, Semi-Conductor Laboratory (SCL), Mohali)
  3. Kanupriya Varshney (Guide: Dr. Brajesh Rawat)
  4. M. A. Saeed (Co-guide: Dr. B. Umapathi, Semi-Conductor Laboratory (SCL), Mohali)
  5. Sahibia Kaur Vohra (Co-guide: Dr. Mahendra Sakare)
  6. Sherin A Thomas (Co-guide: Dr. Rohit Sharma)
  7. Mayank Kumar Singh (Guide: Dr. Mahendra Sakare)

Sponsored research projects

  1. SERB Core Research Grant (2022-25) [Role: PI]
  2. SERB Special Call on Critical Components and Innovations in Oxygen Concentrators (2022-23) [Role: PI]
  3. MeitY funded project on Development of Electric Vehicles (EVs) Sub-Systems (2022-24) [Role: Co-PI]
  4. ISIRD grant funded by IIT Ropar (2019-22) [Role: PI]
  5. IC-IMPACTS project (2019-20). [Role: Co-PI]
  6. 1 completed project funded by industry in 2019. [Role: PI]

Publications

  1. Soniya, Shivdeep, K. K. Jha, D. M. Das, R. Sharma "A Low-Overhead PUF Based Hardware Security Technique to Prevent Scan Chain Attacks for Industry-Standard DFT Architecture," Accepted in 2022 IEEE International Midwest Symposium on Circuits and Systems (MWSCAS), Fukuoka, Japan, 2022.
  2. Shivdeep, S. K. Vohra, N. Goel and D. M. Das, "A Robust Training Signal Generator for Trainable Memristive Digital to Analog Converter," 2021 IEEE International Symposium on Smart Electronic Systems (iSES), 2021, pp. 1-5, doi: 10.1109/iSES52644.2021.00014.
  3. S. Kumar and D. M. Das, "Python-LTspice Co-Simulation to Train Neural Networks with Memristive Synapses to Learn Logic Gate Operations," 2021 IEEE International Symposium on Smart Electronic Systems (iSES), 2021, pp. 147-152, doi: 10.1109/iSES52644.2021.00043.
  4. S. K. Vohra, S. Thomas, M. Sakare and D. M. Das, "Analytical Modelling of a CMOS Inter Spike Interval Decoder for Resistive Crossbar based Brain Inspired Computing," 25th International Symposium on VLSI Design and Test (VDAT), 2021, pp. 1-4, doi: 10.1109/VDAT53777.2021.9600953.
  5. A. Srivastava, D. M. Das and M. S. Baghini, "Design and Implementation of 0.23 nJ/bit Reference-Spur-Free FSK/OOK Transmitter at 400 MHz for Wearable Health Monitoring," 2021 IEEE Biomedical Circuits and Systems Conference (BioCAS), 2021, pp. 1-5, doi: 10.1109/BioCAS49922.2021.9644937.
  6. S. K. Vohra, S. Thomas, M. Sakare and D. M. Das, "Full CMOS Implementation of Bidirectional Associative Memory Neural Network with Analog Memristive Synapse," 2021 IEEE International Midwest Symposium on Circuits and Systems (MWSCAS), 2021, pp. 445-448, doi: 10.1109/MWSCAS47672.2021.9531865.
  7. S. A. Thomas, S. K. Vohra, R. Kumar, R. Sharma and D. M. Das, "Analysis of Parasitics on CMOS based Memristor Crossbar Array for Neuromorphic Systems," 2021 IEEE International Midwest Symposium on Circuits and Systems (MWSCAS), 2021, pp. 309-312, doi: 10.1109/MWSCAS47672.2021.9531867.
  8. S. Das, S. Wadhwa and D. M. Das, "A CMOS based High Resolution All-Digital Temperature Sensor with Low Power Supply Sensitivity," 2021 IEEE International Midwest Symposium on Circuits and Systems (MWSCAS), 2021, pp. 137-140, doi: 10.1109/MWSCAS47672.2021.9531828.
  9. M. K. Singh, P. Singh, D. M. Das and M. Sakare, "A low power 8 X 27 - 1 PRBS using Exclusive-OR gate merged D flip-flops," 2021 IEEE International Midwest Symposium on Circuits and Systems (MWSCAS), 2021, pp. 779-782, doi: 10.1109/MWSCAS47672.2021.9531827.
  10. D .M. Das, K. Barot, A. Srivastava and M. Shojaei Baghini, "Noise-power-area optimised design procedure for OTAs with complementary input transistors for neural amplifiers," in IET Circuits, Devices & Systems, vol. 14, no. 5, pp. 702-706, August 2020, doi: 10.1049/iet-cds.2019.0259.
  11. A. Karmakar, D. M. Das and M. Shojaei Baghini, "Adaptive analogue calibration technique to compensate electrode motion artefacts in biopotential recording," in IET Circuits, Devices & Systems, vol. 14, no. 3, pp. 327-332, May 2020, doi: 10.1049/iet-cds.2019.0409.
  12. D. M. Das, A. Vidwans, A. Srivastava, M. Ahmad, S. Vaishnav, S. Dewan and M. Shojaei Baghini, "Design and development of an Internet-of-Things enabled wearable ExG measuring system with a novel signal processing algorithm for electrocardiogram," in IET Circuits, Devices & Systems, vol. 13, no. 6, pp. 903-907, September 2019, doi: 10.1049/iet-cds.2018.5498.
  13. A. Srivastava, D. M. Das, P. Mathur, D. K. Sharma and M. Shojaei Baghini, "0.43-nJ/bit OOK Transmitter for Wearable and Implantable Devices in 400-MHz MedRadio Band," in IEEE Microwave and Wireless Components Letters, vol. 28, no. 3, pp. 263-265, March 2018, doi: 10.1109/LMWC.2018.2800527.
  14. D. M. Das, A. Gupta, A. Srivastava, A. Vidwans, M. Ahmad, A. Shelke, S. Kale, J. Ananthapadmanabhan, D K Sharma, M. Shojaei Baghini, "A pulse oximeter system, OxiSense, with embedded signal processing using an ultra-low power ASIC designed for testability", Elsevier Microelectronics Journal, Volume 72, 2018, Pages 1-10,ISSN 0026-2692, https://doi.org/10.1016/j.mejo.2017.12.001.
  15. B. Chatterjee, N. Modak, A. Amaravati, D. Mistry, D. M. Das and M. S. Baghini, "A Sub-1 V, 120 nW, PVT-Variation Tolerant, Tunable, and Scalable Voltage Reference With 60-dB PSNA," in IEEE Transactions on Nanotechnology, vol. 16, no. 3, pp. 406-410, May 2017, doi: 10.1109/TNANO.2017.2656161.
  16. D. M. Das, A. Srivastava, A. Gupta, K. Barot and M. S. Baghini, "A noise-power-area optimized novel programmable gain and bandwidth instrumentation amplifier for biomedical applications," 2017 IEEE International Symposium on Circuits and Systems (ISCAS), 2017, pp. 1-4, doi: 10.1109/ISCAS.2017.8050955.
  17. A. Srivastava, N. Sankar, D. M. Das and M. S. Baghini, "LNA-LO Co-design Considerations for Low Intermediate Frequency Receivers in 401-406 MHz MedRadio Spectrum for Healthcare Applications," 2017 30th International Conference on VLSI Design and 2017 16th International Conference on Embedded Systems (VLSID), 2017, pp. 175-180, doi: 10.1109/VLSID.2017.18.
  18. D. M. Das, Abhishek Srivastava, J. Ananthapadmanabhan, Meraj Ahmad, Maryam Shojaei Baghini, "A novel low-noise fully differential CMOS instrumentation amplifier with 1.88 noise efficiency factor for biomedical and sensor applications", Elsevier Microelectronics Journal, Volume 53, 2016, Pages 35-44, ISSN 0026-2692, https://doi.org/10.1016/j.mejo.2016.04.008. (One of the most downloaded papers in 2016)
  19. A. Srivastava, N. Sankar K., B. Chatterjee, D. M. Das, M. Ahmad, Rakesh K. K., V. Saraf, J. Ananthapadmanabhan, D. K. Sharma, and M. Shojaei Baghini, "Bio-WiTel: A Low-Power Integrated Wireless Telemetry System for Healthcare Applications in 401–406 MHz Band of MedRadio Spectrum," in IEEE Journal of Biomedical and Health Informatics, vol. 22, no. 2, pp. 483-494, March 2018, doi: 10.1109/JBHI.2016.2639587.
  20. A. Srivastava, D. M. Das, M. S. Vignesh, K. Bharadwaj, S. Dewan and M. S. Baghini, "Bio-telemetry and bio-instrumentation technologies for healthcare monitoring systems," 2016 IEEE Region 10 Humanitarian Technology Conference (R10-HTC), 2016, pp. 1-6, doi: 10.1109/R10-HTC.2016.7906827.
  21. A. Srivastava, D. M. Das, D. K. Sharma and M. S. Baghini, "SAW resonator oscillator based injection locked OOK transmitter for MedRadio spectrum," 2016 14th IEEE International New Circuits and Systems Conference (NEWCAS), 2016, pp. 1-4, doi: 10.1109/NEWCAS.2016.7604804.
  22. P. Kimtee, D. M. Das and M. S. Baghini, "A mismatch insensitive reconfigurable discrete time biosignal conditioning circuit in 180 nm MM CMOS technology," 2016 20th International Symposium on VLSI Design and Test (VDAT), 2016, pp. 1-2, doi: 10.1109/ISVDAT.2016.8064907.
  23. A. Srivastava, N. Sankar, K. K. Rakesh, B. Chatterjee, D. M. Das and M. S. Baghini, "Design and measurement techniques for a low noise amplifier in a receiver chain for MedRadio spectrum of 401–406 MHz frequency band," 2016 20th International Symposium on VLSI Design and Test (VDAT), 2016, pp. 1-6, doi: 10.1109/ISVDAT.2016.8064846.
  24. D. M. Das, J. Ananthapadmanabhan, M. S. Baghini and D. K. Sharma, "Design considerations for high-CMRR low-power current mode instrumentation amplifier for biomedicai data acquisition systems," 2014 21st IEEE International Conference on Electronics, Circuits and Systems (ICECS), 2014, pp. 251-254, doi: 10.1109/ICECS.2014.7049969.
  25. B. Subrahmanyam, D. M. Das, M. S. Baghini and J. Redoute, "A balanced CMOS OpAmp with high EMI immunity," 2014 International Symposium on Electromagnetic Compatibility, 2014, pp. 703-708, doi: 10.1109/EMCEurope.2014.6930995.

Patents

  1. Inventor in a patent filed on ultra low noise instrumentation amplifier.
  2. Co-inventor in a patent filed on handheld pulse oximeter recording and analysis system.
  3. Co-inventor in a patent filed on a design method for low-power low-noise bio-medical signal conditioning circuit with extracted noise and mis-match parameters.
  4. Co-inventor in a patent filed on voltage mode log domain low-pass filter. [Patent no. 398460; Granted on 02-June-2022.]
  5. Co-inventor in a patent filed on SAW resonator oscillator based injection locked OOK transmitter for health care applications in MedRadio spectrum (401-406 MHz). [Patent no. 381814; Granted on 15-Nov-2021.]
  6. Co-inventor in a patent filed on design considerations for transmitter and receiver for personal health care applications.

Chip gallery and system prototypes developed


Devarshi Das Devarshi Das Devarshi Das Devarshi Das

Technical/Administrative activities

  1. Invited TPC member in VDAT 2022
  2. One of the Track Chair for Analog and Mixed-Signal Design, International VLSI Design (VLSID) Conference 2022
  3. Invited TPC member (Track: Nanoelectronic VLSI and Sensor Systems), IEEE-iSES 2019, IEEE-iSES 2020
  4. CBME MedTech Workshop, IIT Ropar, 2019, Evaluation panel member
  5. Faculty advisor: 1) EE 2019 UG batch; 2) M.Tech (VLSI) 2020 batch
  6. Ph.D (VLSI) coordinator (Feb. 2020 - onwards)
  7. Reviewer: IEEE Trans. Circuits and Systems - 1, IEEE Trans. on Instrumentation and Measurements, IEEE Trans. on Neural Networks and Learning Systems, IEEE Trans. on Biomedical Circuits and Systems, IEEE Systems Journal, Elsevier Microelectronics Journal, Elsevier Sensors and Actuators, and others.

Invited Talks

  1. Short-term course on Analog and Digital VLSI Design at National Institute of Technical Teacher Training and Research (NITTTR), Chandigarh (Sept., 2021)
  2. ReAp@CVEST-2020, 1-day workshop at IIIT Hyderabad (Oct., 2020)
  3. APJ Abdul Kalam Faculty Lecture Series at IIT Ropar (Oct., 2020)

Awards and Honors

  1. 2019 IEEE Trans. on Instrumentation and Measurements Outstanding Reviewer. (Feb. 2020)
  2. IEEE ISCAS 2017 - Student Travel Grant. (May 2017)
  3. SERB International Travel Support (ITS). (May 2017)
  4. TCS fellowship through VLSI Design Lab, IIT Bombay. (September 2016 - May 2017)
  5. Research sponsorship from Ministry of Electronics and Information Technology(MeitY), Govt. of India. (July 2012- August 2016)
  6. Scholarship from Ministry of Human Resource Development (MHRD), Govt. of India for post-graduate studies. (2008-2010)

MTP Students

  1. Shivangi Gupta (2022-23) (Co-guide: Dr. Neeraj Goel) [Intern at Synopsis]
  2. Mayuri (2022-23) (Co-guide: Dr. Neeraj Goel) [Intern at Synopsis]
  3. Jateen Dalbehera (2021-22) [Joined Intel]
  4. Soumyashib Das (2020-21) [Joined NXP Semiconductors]
  5. Dulumoni Pegu (2020-21) [Joined Cadence Design Systems]

BTP Students

  1. Varun Sharma (2021-22) [Joined Texas Instruments.]
  2. Aman Kumar (2021-22) [Applying to pursue higher studies.]
  3. Mitali Rathod (2020-21) [Joined Ceremorphic. Currently at Nvidia.]
  4. Nikhil Jain (2020-21) [Joined SignalChip.]
  5. Shreshtha Gothalyan (2019-20) [Joined HPCL.]
  6. Anil Kumar Panda (2018-19) [Joined M.Tech. program at IITK.]
  7. Gaurav Kamila (2018-19) [Joined M.Tech. program at IITB. Currently in MediaTek, Taiwan.]

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