Devarshi Das, IIT Ropar

Research interests

CMOS circuits and systems for neuromorphic computing
Cryo-CMOS circuits and systems for quantum computing
EMI immune CMOS circuits and systems for 6G ecosystem
Quantum package interfacing IC for chip-scale atomic clock

About me

I am an assistant professor in the Department of Electrical Engineering and an associate faculty member at the newly constituted School of Artificial Intelligence and Data Engineering at IIT Ropar. My teaching and research interests include Analog, Mixed-Signal and RF integrated circuit design for futuristic applications in computing and sensing. I am a senior member of IEEE and an active reviewer for many reputed journals. Additionally, I am the PhD coordinator for the Microelectronics and VLSI Design group. I direct the Integrated System Design Lab (ISDL) at IIT Ropar where we do cutting-edge research on Integrated Circuit Design. Our research outcomes are well documented in various patents, reputed journal publications and conference proceedings. Our research is funded by research sponsors such as the Anusandhan National Research Foundation (ANRF), the Ministry of Electronics and Information Technology (MeitY) of the Government of India and generous support from IIT Ropar. My team members are highly passionate about technology and are self-motivated. Each day, we strive to achieve excellence through hard work, grit and perseverance. I am always looking for highly motivated candidates interested in developing skills in Integrated Circuit Design for PhD or PG/UG capstone project.

Academic background

Ph.D., Indian Institute of Technology Bombay (IIT-B), Mumbai, India (2012-17)
M.Tech., Indian Institute of Technology Delhi (IIT-D), New Delhi, India (2008-10)
B.E., Faculty of Technology, Dharmsinh Desai University (DDU), Gujarat, India (2002-06)

Work experience

Indian Institute of Technology Ropar, Assistant Professor, 2018 - onwards
Siemens, Lead Research Engineer, 2017-18
General Electric, Design Engineer, 2010-12

Graduated Ph.D. Scholar

Dr. Sahibia Kaur Vohra (Graduated in 2025, Guides: Devarshi Mrinal Das and Mahendra Sakare) Joined Forschungszentrum Jülich, Germany. Link: More details

Publications

2025

Nidhi, S. A. Thomas, V. G. Hande, D. M. Das, "A Modified Three Stage Dynamic Comparator Achieving Rail-to-Rail Input Common-mode Range with <86 fJ.ns EDP", in IEEE Transactions on Circuits and Systems II: Express Briefs, 2025. (under minor revision)
Nidhi, A. Pratap, D. M. Das, P. A. Husing, "Intelligent Analog and Mixed-Signal IC (I-AMS-IC) Design: A Conceptual Framework, and Case Study on AI Integration", Accepted in IEEE International Symposium on Computer, Consumer and Control, Taichung, Taiwan, 2025.
Shivdeep, S. Boyapati, D. M. Das, "Impact of EMI on the Reliability of Crossbar Architecture-based Inference in CMOS Technology," in IEEE Transactions on Components, Packaging and Manufacturing Technology, April, 2025, doi: 10.1109/TCPMT.2025.3559486.
S. K. Vohra, M. Sakare, A. P. James, D. M. Das, "SpiMAM: CMOS Implementation of Bio-Inspired Spiking Multidirectional Associative Memory Featuring In-Situ Learning," in IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 72, no. 1, pp. 2-13, Jan. 2025, doi: 10.1109/TCSI.2024.3427387.
N. Sharma, R. K. Srivastava, D. Sehgal, D. M. Das, "A low-power common-mode insensitive rail-to-rail dynamic comparator for ADCs", Integration, Volume 100, 2025, 102288, ISSN 0167-9260, https://doi.org/10.1016/j.vlsi.2024.102288.
M. K. Singh, M. Bhuvanesh, R. Nagulapalli, D. M. Das, M. Sakare, "A 2.9 mW Inverter-based Quadrature Phase Clock Generator with ± 0.29° Phase Error", Accepted in IEEE ISCAS 2025, London, UK.

2024

S. A. Thomas, S. Kushwaha, R. Sharma, D. M. Das, "Design and Analysis of 3D Integrated Folded Ferro-Capacitive Crossbar Array (FC²A) for Brain-Inspired Computing System," in IEEE Journal on Emerging and Selected Topics in Circuits and Systems, vol. 14, no. 3, pp. 563-574, Sept. 2024, doi: 10.1109/JETCAS.2024.3432458.
N. Sharma, V. Hande, D. M. Das, "A Dynamic Comparator With Cross-Coupled Pre-Amplifier With <160 ps Delay and 81 fJ.ns EDP," in Integrated Circuits and Systems, vol. 1, no. 4, pp. 206-213, Sept.-Oct. 2024, doi: 10.23919/ICS.2024.3505092.
S. K. Vohra, S. A. Thomas, M. Sakare, D. M. Das, "Circuit Implementation of On-chip Trainable Spiking Neural Network using CMOS Based Memristive STDP Synapses and LIF Neurons," Integration, the VLSI Journal, Volume 95, 2024, 102122, ISSN 0167-9260, doi: 10.1016/j.vlsi.2023.102122.
K. Varshney, P. Shukla, B. Prakash, D. M. Das, B. Rawat, "Enhancing Resistive Switching Characteristics of MoS₂-based Memristor through O₂ Plasma Irradiation-Induced Defects," in IEEE Journal of the Electron Devices Society, doi: 10.1109/JEDS.2024.3480356.
S. A. Thomas, S. Kushwaha, R. Sharma, D. M. Das, "Modeling and Comparing the Impact of Resistive and Capacitive Crossbar Associated Parasitics of Neuromorphic Circuits," 2024 31st International Conference on Mixed Design of Integrated Circuits and System (MIXDES), Gdansk, Poland, 2024, pp. 171-176, doi: 10.23919/MIXDES62605.2024.10614061. [Received Best Paper Award]
D. Chowdhury, Shivdeep, D. M. Das, "A Pulse Oximeter and a Controller Designed for Automatic Regulation of Oxygen Concentrators," 2024 37th International Conference on VLSI Design and 2024 23rd International Conference on Embedded Systems (VLSID), Kolkata, India, 2024, pp. 336-341, doi: 10.1109/VLSID60093.2024.00062.
S. Bhaskara, S. Girishan K. V., S. Datta, S. Gupta, K. Lakshmiramanan, D. M. Das, H. J. Pandya, "A Novel Charge Neutral, Programmable, Wireless Brain Stimulation System for Rat Experiments," 2024 8th International Conference on Biomedical Engineering and Applications (ICBEA), Tokyo, Japan, 2024, pp. 124-130, doi: 10.1109/ICBEA62825.2024.00031.
S. Sharma, Shivdeep, N. Sharma, D. M. Das, "A 0.006 mm² Low Input Capacitance Low Power Fully Differential Neural Amplifier," 2024 31st International Conference on Mixed Design of Integrated Circuits and System (MIXDES), Gdansk, Poland, 2024, pp. 50-54, doi: 10.23919/MIXDES62605.2024.10613933.
A. Yaseen N. J., Shivdeep, S. Sharma, H. Shrimali, D. M. Das, "A 66dBΩ 5 GHz and 44.88 √Hz/(pA·pW) Inductorless TIA in 65 nm CMOS," 2024 31st International Conference on Mixed Design of Integrated Circuits and System (MIXDES), Gdansk, Poland, 2024, pp. 55-60, doi: 10.23919/MIXDES62605.2024.10613986.
N. Sharma, S. Sharma, D. M. Das, "A 66 μW Asynchronous Time-Domain Bulk-Tuned Offset Cancellation Circuit for High-Precision Dynamic Comparator," 2024 31st International Conference on Mixed Design of Integrated Circuits and System (MIXDES), Gdansk, Poland, 2024, pp. 61-67, doi: 10.23919/MIXDES62605.2024.10613940.
K. Varshney, R. Sharma, D. M. Das and B. Rawat, "Performance of Plasma Treated 2D MoS₂ Synaptic Memristor for Neuromorphic Computing", Accepted in IEEE EDAPS 2024, Bengaluru, India.
S. Kushwaha, S. Roy, D. M. Das and R. Sharma, "Signal Integrity Analysis of Ultra-scaled Copper-Graphene Heterogeneous Interconnect Structures", Accepted in IEEE EDAPS 2024, Bengaluru, India.
M. K. Singh, R. Nagulapalli, D. M. Das, M. Sakare, "An RC-Based Dual Injection Locked Delay Cell for High-Frequency Ring VCOs," 2024 35th Irish Signals and Systems Conference (ISSC), Belfast, United Kingdom, 2024, pp. 1-6, doi: 10.1109/ISSC61953.2024.10603085.
M. K. Singh, H. Mehra, T. Kaur, R. Nagulapalli, D. M. Das, M. Sakare, "A 15.4 ppm/°C Improved Current Mode Bandgap with 0.9 V Supply in 28 nm CMOS," 2024 International Conference on Integrated Circuits, Communication, and Computing Systems (ICIC3S), Una, India, 2024, pp. 1-5, doi: 10.1109/ICIC3S61846.2024.10603389.
K. Varshney, P. Shukla, B. Prakash, D. M. Das, B. Rawat, "Improved Resistive Switching and Synaptic characteristics on 2-D Graphene/MoS2/Graphene Memristor using O2 Plasma Irradiation," 2024 8th IEEE Electron Devices Technology & Manufacturing Conference (EDTM), Bangalore, India, 2024, pp. 1-3, doi: 10.1109/EDTM58488.2024.10511881.
K. Varshney, M. S. Yadav, D. M. Das, B. Rawat, "Finding a Promising Oxide Material for Resistive Random Access Memory with Graphene Electrode," 2024 37th International Conference on VLSI Design and 2024 23rd International Conference on Embedded Systems (VLSID), Kolkata, India, 2024, pp. 414-418, doi: 10.1109/VLSID60093.2024.00075.

2023

S. K. Vohra, S. A. Thomas, Shivdeep, M. Sakare and D. M. Das, "Full CMOS Circuit for Brain-Inspired Associative Memory With On-Chip Trainable Memristive STDP Synapse," in IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 31, no. 7, pp. 993-1003, July 2023, doi: 10.1109/TVLSI.2023.3268173.
M. A. Saeed, M. Kumar, B. Umapathi, D. M. Das, "Optimization of Slew Mitigation Capacitor in Passive Charge Compensation-Based Delta–Sigma Modulator," in IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 70, no. 6, pp. 1821-1825, June 2023, doi: 10.1109/TCSII.2023.3234909.
K. Varshney, M. S. Yadav, B. Rawat, D. M. Das, "Analysis and Modeling of Bipolar Resistive Switching in 2-D Graphene Electrode- Based Memristor," in IEEE Transactions on Electron Devices, vol. 70, no. 10, pp. 5454-5461, Oct. 2023, doi: 10.1109/TED.2023.3308525.
M. A. Saeed, R. K. Srivastava, D. Sehgal, D. M. Das, "Design of a High Precision CMOS Programmable Gain and Data Rate Delta Sigma ADC", Analog Integr Circ Sig Process (2023), doi: 10.1007/s10470-023-02165-9.
S. A. Thomas, R. Sharma, D. M. Das, "Analyzing the impact of parasitics on a CMOS-Memristive crossbar neural network based on winner-take-all and Hebbian rule", Memories - Materials, Devices, Circuits and Systems, 2023, 100081, ISSN 2773-0646, https://doi.org/10.1016/j.memori.2023.100081.
M. K. Singh, P. Singh, U. Chichhula, H. Mehra, D. M. Das, M. Sakare, "A PRBS Generator using Merged XOR-D flip-flop as Building Blocks", Circuits, Systems & Signal Processing (Springer, CSSP), 2023, doi: 10.1007/s00034-023-02425-z.
S. K. Vohra, M. Sakare, D. M. Das, "Full CMOS Analog Circuit Implementation of Multi-Functional Pavlov Associative Memory using STDP Learning," 2023 IEEE Women in Technology Conference (WINTECHCON), Bangalore, India, 2023, pp. 1-6, doi: 10.1109/WINTECHCON58518.2023.10277203. [Received Best Paper Award]
M. K. Singh, P. Singh, D. M. Das and M. Sakare, "A Low Power Differential Delay Cell without Cross-Coupled Latch for Ring VCO," 2023 18th Conference on Ph.D Research in Microelectronics and Electronics (PRIME), Valencia, Spain, 2023, pp. 145-148, doi: 10.1109/PRIME58259.2023.10161983. [Received "Gold leaf certificate" Best Paper Award.]
Shivdeep, S. Sharma, S. Boyapati, D. M. Das, "A Two Stage Miller OpAmp with Low Voltage Cascode Current Source with High EMI Immunity," 2023 International Symposium on Electromagnetic Compatibility – EMC Europe, Krakow, Poland, 2023, pp. 1-6, doi: 10.1109/EMCEurope57790.2023.10274391.
N. Sharma, R. K. Srivastava, V. Hande, D. Sehgal, D. M. Das, "A Self-Calibration Logic Circuit Agnostic To Offset Calibration Technique For High-Precision Dynamic Comparator," 2023 IEEE Women in Technology Conference (WINTECHCON), Bangalore, India, 2023, pp. 1-6, doi: 10.1109/WINTECHCON58518.2023.10277170.
S. A. Thomas, S. K. Vohra, S. Kushwaha, R. Sharma, D. M. Das, "Modeling and Analysis of CMOS-based Folded Memristive Crossbar Array for 3D Neuromorphic Integrated Circuits," 2023 IEEE 73rd Electronic Components and Technology Conference (ECTC), Orlando, FL, USA, 2023, pp. 960-966, doi: 10.1109/ECTC51909.2023.00164.
S. K. Vohra, A. P. James, M. Sakare, D. M. Das, "Analysing Mismatch effect of CMOS Neurons in Spiking Neural Network with Winner-take-all Mechanism," 2023 IEEE Nordic Circuits and Systems Conference (NorCAS), Aalborg, Denmark, 2023, pp. 1-7, doi: 10.1109/NorCAS58970.2023.10305471.
M. K. Singh, M. K. Gautam, P. Singh, R. Nagulapalli, D. M. Das and M. Sakare, "A Double Cross-Coupled Delay Cell for High-Frequency Differential Ring VCOs," 2023 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), Hyderabad, India, 2023, pp. 1-5, doi: 10.1109/APCCAS60141.2023.00013.

2022

S. A. Thomas, S. K. Vohra, R. Kumar, R. Sharma, D. M. Das, "Analysis of Parasitic Effects in a Crossbar in CMOS Based Neuromorphic System for Pattern Recognition Using Memristive Synapses", in IEEE Transactions on Nanotechnology, Special Section on “Neuromorphic Computing”, 2022, doi: 10.1109/TNANO.2022.3190903.
N. Sharma, V. Hande, R. K. Srivastava, D. M. Das, "6-bit 1-GS/s Partially Active Flash ADC with Comparator Offset Correction," 2022 IEEE International Symposium on Smart Electronic Systems (iSES), Warangal, India, 2022, pp. 465-470, doi: 10.1109/iSES54909.2022.00101.
K. Varshney, M. S. Yadav, D. M. Das, B. Rawat, "Performance of Graphene Oxide-based Memristor for Nonvolatile Memory and Neuromorphic Computing," 2022 IEEE International Conference on Emerging Electronics (ICEE), Bangalore, India, 2022, pp. 1-6, doi: 10.1109/ICEE56203.2022.10118104.
S. Chittoriya, Shivdeep, K. K. Jha, D. M. Das, R. Sharma, "A Low-Overhead PUF Based Hardware Security Technique to Prevent Scan Chain Attacks for Industry-Standard DFT Architecture", 2022 IEEE 65th International Midwest Symposium on Circuits and Systems (MWSCAS), 2022, pp. 1-4, doi: 10.1109/MWSCAS54063.2022.9859268.
K. Poojith, K. Varshney, M. S. Yadav, D. M. Das, B. Rawat, "Modulation of Resistive Switching Behaviour of TaOx-based Memristor Through Device Engineering", 2022 IEEE 7th International conference for Convergence in Technology (I2CT), 2022, pp. 1-6, doi: 10.1109/I2CT54291.2022.9824458.

2021 and before

Shivdeep, S. K. Vohra, N. Goel, D. M. Das, "A Robust Training Signal Generator for Trainable Memristive Digital to Analog Converter", 2021 IEEE International Symposium on Smart Electronic Systems (iSES), 2021, pp. 1-5, doi: 10.1109/iSES52644.2021.00014.
S. Kumar, D. M. Das, "Python-LTspice Co-Simulation to Train Neural Networks with Memristive Synapses to Learn Logic Gate Operations", 2021 IEEE International Symposium on Smart Electronic Systems (iSES), 2021, pp. 147-152, doi: 10.1109/iSES52644.2021.00043.
S. K. Vohra, S. A. Thomas, M. Sakare, D. M. Das, "Analytical Modelling of a CMOS Inter Spike Interval Decoder for Resistive Crossbar based Brain Inspired Computing", 25th International Symposium on VLSI Design and Test (VDAT), 2021, pp. 1-4, doi: 10.1109/VDAT53777.2021.9600953.
A. Srivastava, D. M. Das, M. S. Baghini, "Design and Implementation of 0.23 nJ/bit Reference-Spur-Free FSK/OOK Transmitter at 400 MHz for Wearable Health Monitoring", 2021 IEEE Biomedical Circuits and Systems Conference (BioCAS), 2021, pp. 1-5, doi: 10.1109/BioCAS49922.2021.9644937 (selected as one of the top contributions to the conference).
S. K. Vohra, S. Thomas, M. Sakare, D. M. Das, "Full CMOS Implementation of Bidirectional Associative Memory Neural Network with Analog Memristive Synapse", 2021 IEEE International Midwest Symposium on Circuits and Systems (MWSCAS), 2021, pp. 445-448, doi: 10.1109/MWSCAS47672.2021.9531865.
S. A. Thomas, S. K. Vohra, R. Kumar, R. Sharma, D. M. Das, "Analysis of Parasitics on CMOS based Memristor Crossbar Array for Neuromorphic Systems", 2021 IEEE International Midwest Symposium on Circuits and Systems (MWSCAS), 2021, pp. 309-312, doi: 10.1109/MWSCAS47672.2021.9531867.
S. Das, S. Wadhwa, D. M. Das, "A CMOS based High Resolution All-Digital Temperature Sensor with Low Power Supply Sensitivity", 2021 IEEE International Midwest Symposium on Circuits and Systems (MWSCAS), 2021, pp. 137-140, doi: 10.1109/MWSCAS47672.2021.9531828.
M. K. Singh, P. Singh, D. M. Das, M. Sakare, "A low power 8 X 2⁷ - 1 PRBS using Exclusive-OR gate merged D flip-flops", 2021 IEEE International Midwest Symposium on Circuits and Systems (MWSCAS), 2021, pp. 779-782, doi: 10.1109/MWSCAS47672.2021.9531827.
D. M. Das, K. Barot, A. Srivastava, M. S. Baghini, "Noise-power-area optimised design procedure for OTAs with complementary input transistors for neural amplifiers", in IET Circuits, Devices & Systems, vol. 14, no. 5, pp. 702-706, August 2020, doi: 10.1049/iet-cds.2019.0259.
A. Karmakar, D. M. Das, M. S. Baghini, "Adaptive analogue calibration technique to compensate electrode motion artefacts in biopotential recording", in IET Circuits, Devices & Systems, vol. 14, no. 3, pp. 327-332, May 2020, doi: 10.1049/iet-cds.2019.0409.
D. M. Das, A. Vidwans, A. Srivastava, M. Ahmad, S. Vaishnav, S. Dewan and M. Shojaei Baghini, "Design and development of an Internet-of-Things enabled wearable ExG measuring system with a novel signal processing algorithm for electrocardiogram", in IET Circuits, Devices & Systems, vol. 13, no. 6, pp. 903-907, September 2019, doi: 10.1049/iet-cds.2018.5498.
A. Srivastava, D. M. Das, P. Mathur, D. K. Sharma, M. S. Baghini, "0.43-nJ/bit OOK Transmitter for Wearable and Implantable Devices in 400-MHz MedRadio Band", in IEEE Microwave and Wireless Components Letters, vol. 28, no. 3, pp. 263-265, March 2018, doi: 10.1109/LMWC.2018.2800527.
D. M. Das, A. Gupta, A. Srivastava, A. Vidwans, M. Ahmad, A. Shelke, S. Kale, J. Ananthapadmanabhan, D K Sharma, M. Shojaei Baghini, "A pulse oximeter system, OxiSense, with embedded signal processing using an ultra-low power ASIC designed for testability", Elsevier Microelectronics Journal, Volume 72, 2018, Pages 1-10,ISSN 0026-2692, https://doi.org/10.1016/j.mejo.2017.12.001.
B. Chatterjee, N. Modak, A. Amaravati, D. Mistry, D. M. Das, M. S. Baghini, "A Sub-1 V, 120 nW, PVT-Variation Tolerant, Tunable, and Scalable Voltage Reference With 60-dB PSNA", in IEEE Transactions on Nanotechnology, vol. 16, no. 3, pp. 406-410, May 2017, doi: 10.1109/TNANO.2017.2656161.
D. M. Das, A. Srivastava, A. Gupta, K. Barot, M. S. Baghini, "A noise-power-area optimized novel programmable gain and bandwidth instrumentation amplifier for biomedical applications", 2017 IEEE International Symposium on Circuits and Systems (ISCAS), 2017, pp. 1-4, doi: 10.1109/ISCAS.2017.8050955.
A. Srivastava, N. Sankar, D. M. Das, M. S. Baghini, "LNA-LO Co-design Considerations for Low Intermediate Frequency Receivers in 401-406 MHz MedRadio Spectrum for Healthcare Applications", 2017 30th International Conference on VLSI Design and 2017 16th International Conference on Embedded Systems (VLSID), 2017, pp. 175-180, doi: 10.1109/VLSID.2017.18.
D. M. Das, A. Srivastava, J. Ananthapadmanabhan, M. Ahmad, M. S. Baghini, "A novel low-noise fully differential CMOS instrumentation amplifier with 1.88 noise efficiency factor for biomedical and sensor applications", Elsevier Microelectronics Journal, Volume 53, 2016, Pages 35-44, ISSN 0026-2692, https://doi.org/10.1016/j.mejo.2016.04.008. (One of the most downloaded papers in 2016)
A. Srivastava, N. Sankar K., B. Chatterjee, D. M. Das, M. Ahmad, Rakesh K. K., V. Saraf, J. Ananthapadmanabhan, D. K. Sharma, M. S. Baghini, "Bio-WiTel: A Low-Power Integrated Wireless Telemetry System for Healthcare Applications in 401–406 MHz Band of MedRadio Spectrum", in IEEE Journal of Biomedical and Health Informatics, vol. 22, no. 2, pp. 483-494, March 2018, doi: 10.1109/JBHI.2016.2639587.
A. Srivastava, D. M. Das, M. S. Vignesh, K. Bharadwaj, S. Dewan and M. S. Baghini, "Bio-telemetry and bio-instrumentation technologies for healthcare monitoring systems", 2016 IEEE Region 10 Humanitarian Technology Conference (R10-HTC), 2016, pp. 1-6, doi: 10.1109/R10-HTC.2016.7906827.
A. Srivastava, D. M. Das, D. K. Sharma, M. S. Baghini, "SAW resonator oscillator based injection locked OOK transmitter for MedRadio spectrum", 2016 14th IEEE International New Circuits and Systems Conference (NEWCAS), 2016, pp. 1-4, doi: 10.1109/NEWCAS.2016.7604804.
P. Kimtee, D. M. Das, M. S. Baghini, "A mismatch insensitive reconfigurable discrete time biosignal conditioning circuit in 180 nm MM CMOS technology", 2016 20th International Symposium on VLSI Design and Test (VDAT), 2016, pp. 1-2, doi: 10.1109/ISVDAT.2016.8064907.
A. Srivastava, N. Sankar, K. K. Rakesh, B. Chatterjee, D. M. Das, M. S. Baghini, "Design and measurement techniques for a low noise amplifier in a receiver chain for MedRadio spectrum of 401–406 MHz frequency band", 2016 20th International Symposium on VLSI Design and Test (VDAT), 2016, pp. 1-6, doi: 10.1109/ISVDAT.2016.8064846.
D. M. Das, J. Ananthapadmanabhan, M. S. Baghini, D. K. Sharma, "Design considerations for high-CMRR low-power current mode instrumentation amplifier for biomedicai data acquisition systems", 2014 21st IEEE International Conference on Electronics, Circuits and Systems (ICECS), 2014, pp. 251-254, doi: 10.1109/ICECS.2014.7049969.
B. Subrahmanyam, D. M. Das, M. S. Baghini and J. Redoute, "A balanced CMOS OpAmp with high EMI immunity", 2014 International Symposium on Electromagnetic Compatibility, 2014, pp. 703-708, doi: 10.1109/EMCEurope.2014.6930995.

Patents

Indian Patent Application No. 202511026465, "A crossbar interfacing circuit immune to electromagnetic interference (EMI)", Shivdeep, S. Sharma, D. M. Das.
Indian Patent Application No. 202411054405, "A neuron circuit and method of operation thereof", S. K. Vohra, S. A. Thomas, M. S. Sakare, D. M. Das.
Indian Patent 565891, "A 3-D Folded Capacitive Crossbar Array System", S. A. Thomas, S. K. Vohra, R. S. Sharma, D. M. Das, Date of Grant: 01 May 2025.
Indian Patent 473407, "Ultra Low Noise Instrumentation Amplifier", D. M. Das and M. S. Baghini, Date of Grant: November 2023.
Indian Patent 498947, "A handheld pulse oximeter system", A. Gupta, D. M. Das, M. S. Baghini, et. al., Date of Grant: January 2024.
Indian Patent 408593, “A Design Method for Low Power and Low Noise Biomedical Signal Conditioning Circuit”, K. J. Barot, D. M. Das and M. S. Baghini, Date of Grant: October 2022.
Indian Patent 398460, “Voltage Mode Log Domain Low Pass Filter (LDLPF) for Healthcare Applications”, J. Ananthapadmanabhan, D. M. Das and M. S. Baghini, Date of Grant: June 2022.
Indian Patent 381814, “SAW Resonator Oscillator Based Injection Locked OOK Transmitter for Healthcare Applications”, A. Srivastava, D. M. Das and M. S. Baghini, Date of Grant: November 2021.
Indian Patent 408641, “Design Considerations for Transmitter and Receiver for Personal Healthcare Applications”, A. Srivastava, N. S. Karuthedath, B. Chaterjee, M. Ahmad, R. K. Kukkundoor, D. M. Das, V. Saraf, J. AnanthPadmanabhan, D. K. Sharma and M. S. Baghini, Date of Grant: October 2022.
US patent 11,774,496, “Pseudo-random binary sequences (PRBS) generator for performing on-chip testing and a method thereof”, M. Sakare, M. K. Singh, P. Singh, D. M. Das, and V. G. Hande, US patent 17/578,526 filed on 19 Jan 2022, granted (US 11,774,496) on 13 Sept 2023.

Contact

Email: firstname.lastname@iitrpr.ac.in

Last update: 14-May-2025